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| WEDNESDAY, June 9, 2004, 4:30 PM - 6:30 PM | Room: 6D | ||
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TOPIC AREA: LOGIC DESIGN AND TEST | ||
| SESSION 34 | |||
| Latency Tolerance and Asynchronous Design | |||
| Chair: Marios Papaefthymiou - Univ. of Michigan, Ann Arbor, MI | |||
| Organizers: James C. Hoe, Leon Stok | |||
| This session presents five papers in the areas of latency tolerance and asynchronous design. The first paper describes a technique to automatically correct the functionality of wire-pipelined circuits. The second paper describes an approach to minimizing the latency management overhead in statically schedulable designs. The third paper proposes approaches to estimate wire length and congestions during logic synthesis. The fourth paper presents optimizations to asynchronous logic synthesis by "de-synchronization". The final paper presents a fast algorithm for hazard detection in combinational circuits. | |||
 34.1 |
A Method for Correcting the Functionality of a Wire-Pipelined Circuit |
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| Speaker(s): | Vidyasagar Nookala - Univ. of Minnesota, Minneapolis, MN | ||
| Author(s): | Vidyasagar Nookala - Univ. of Minnesota, Minneapolis, MN Sachin S. Sapatnekar - Univ. of Minnesota, Minneapolis, MN | ||
| 34.2 | A New Approach to Latency Insensitive Design | ||
| Speaker(s): | Luca Macchiarulo - Politecnico di Torino, Torino, Italy | ||
| Author(s): | Luca Macchiarulo - Politecnico di Torino, Torino, Italy Mario R. Casu - Politecnico di Torino, Torino, Italy | ||
| 34.3 | Pre-Layout Wire Length and Congestion Estimation | ||
| Speaker(s): | Qinghua Liu - Univ. of California, Santa Barbara, CA | ||
| Author(s): | Qinghua Liu - Univ. of California, Santa Barbara, CA Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA | ||
| 34.4s | The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications | ||
| Speaker(s): | Abhijit Davare - Univ. of California, Berkeley, CA | ||
| Author(s): | Abhijit Davare - Univ. of California, Berkeley, CA Kelvin Lwin - Cadence Design Systems, Inc., San Jose, CA Alex Kondratyev - Cadence Berkeley Labs., Berkeley, CA Alberto L. Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA | ||
| 34.5s | Fast Hazard Detection in Combinational Circuits | ||
| Speaker(s): | Cheoljoo Jeong - Columbia Univ., New York, NY | ||
| Author(s): | Cheoljoo Jeong - Columbia Univ., New York, NY Steven M. Nowick - Columbia Univ., New York, NY | ||
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